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SN74LV8T164MPWREP

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Mouser No:

595-74LV8T164MPWREP

Mfr. No:

SN74LV8T164MPWREP

Mfr.:

Texas Instruments

Description:

Counter Shift Registers

Lifecycle:

New Product:

New from this manufacturer.

Datasheet:

SN74LV8T164MPWREP Datasheet

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Learn more about Texas Instruments SN74LV8T164MPWREP

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Texas Instruments
Product Category:	Counter Shift Registers
Delivery Restriction:	Mouser does not presently sell this product in your region.
RoHS:
Counter Type:	Shift Registers
Counting Sequence:	Parallel to Serial
Number of Circuits:	8 Circuit
Number of Bits:	8 bit
Package/Case:	TSSOP-14
Logic Type:	CMOS
Number of Input Lines:	4 Input
Propagation Delay Time:	40.1 ns
Supply Voltage - Min:	1.8 V
Supply Voltage - Max:	5.5 V
Minimum Operating Temperature:	- 55 C
Maximum Operating Temperature:	+ 125 C
Packaging:	Reel
Packaging:	Cut Tape
Packaging:	MouseReel
Brand:	Texas Instruments
Country of Assembly:	MY
Country of Diffusion:	US
Country of Origin:	MY
High Level Output Current:	- 24 mA
Input Type:	Serial
Low Level Output Current:	24 mA
Mounting Style:	SMD/SMT
Number of Output Lines:	9 Output
Operating Supply Voltage:	1.8 V to 5.5 V
Product:	Serial Shift Registers
Product Type:	Counter Shift Registers
Factory Pack Quantity:	3000
Subcategory:	Logic ICs

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Datasheet

SN74LV8T164MPWREP Datasheet

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TARIC:: 8542319000
USHTS:: 8542390090
MXHTS:: 8542399999
ECCN:: EAR99

SN74LV8T164/SN74LV8T164-Q1 Shift Register

Texas Instruments SN74LV8T164/SN74LV8T164-Q1 Parallel-Load Shift Register contains an 8-bit shift register with asynchronous clear (CLR) input and AND-gated serial inputs. The gated serial (A and B) inputs permit complete control over incoming data. A low at either input inhibits new data entry and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, determining the first flip-flop's state. The data at the serial inputs can be changed while CLK is low or high, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.