LMK1D2104RHDT

Texas Instruments
595-LMK1D2104RHDT
LMK1D2104RHDT

Mfr.:

Description:
Clock Buffer Dual bank 4-channel output 1.8-V 2.5-V L LMK1D2104RHDR

Datasheet:
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In Stock: 155

Stock:
155 Can Dispatch Immediately
Factory Lead Time:
6 Weeks Estimated factory production time for quantities greater than shown.
Minimum: 1   Multiples: 1
Unit Price:
€-.--
Ext. Price:
€-.--
Est. Tariff:
Packaging:
Full Reel (Order in multiples of 250)

Pricing (EUR)

Qty. Unit Price
Ext. Price
Cut Tape / MouseReel™ †
€11.85 €11.85
€10.07 €100.70
Full Reel (Order in multiples of 250)
€7.26 €1,815.00
€6.97 €3,485.00
€6.87 €6,870.00
† A MouseReel™ fee of €5.00 will be added and calculated in your basket. All MouseReel™ orders are non-cancellable and non-returnable. ↩

Alternative Packaging

Mfr. Part No.:
LMK1D2104RHDR
Packaging:
Reel, Cut Tape, MouseReel
Availability:
In Stock
Price:
€9.50
Min:
1

Product Attribute Attribute Value Select Attribute
Texas Instruments
Product Category: Clock Buffer
RoHS:  
4 Output
2 GHz
575 ps
LVDS
VQFN-28
HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
2 GHz
1.71 V
3.465 V
LMK1D2104
- 40 C
+ 105 C
Brand: Texas Instruments
Country of Assembly: Not Available
Country of Diffusion: Not Available
Country of Origin: CN
Duty Cycle - Max: 55 %
Moisture Sensitive: Yes
Mounting Style: SMD/SMT
Packaging: Reel
Packaging: Cut Tape
Packaging: MouseReel
Product: Clock Buffers
Product Type: Clock Buffers
Factory Pack Quantity: 250
Subcategory: Clock & Timer ICs
Type: Low Additive Jitter LVDS Buffer
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Attributes selected: 0

Datasheet

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CNHTS:
8542399000
CAHTS:
8542390000
USHTS:
8542390090
MXHTS:
8542399999
ECCN:
EAR99

LMK1D210x Low Additive Jitter LVDS Buffer

Texas Instruments LMK1D210x Low Additive Jitter LVDS Buffer distributes two clock inputs (IN0 and IN1) to a total of up to 8 pairs of differential LVDS clock outputs (OUT0, OUT7) with minimum skew for clock distribution. Each buffer block consists of one input and up to 4 LVDS outputs. The inputs can be LVDS, LVPECL, HCSL, CML, or LVCMOS. The LMK1D210x is specifically designed for driving 50Ω transmission lines. In the case of driving the inputs in single-ended mode, the appropriate bias voltage must be applied to the unused negative input pin.

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